The present invention relates in general to latching ccmparators and in particular to a latching comparator capable of high frequency operation.
Latching comparators generate a digital output signal indicating when an applied input voltage exceeds an applied reference voltage at the end of a first portion of an applied clocking signal, the output signal being latched in its current state during a second portion of the clocking signal. Latching comparators of the prior art typically include an input differential amplifier stage driving a latching amplifier stage, wherein the latter is provided with positive feedback. During the first portion of the clock cycle, bias current is provided to the input stage, while in a second portion of the clock cycle bias current is switched to the latching amplifier leaving the input amplifier de-energized.
One problem associated with such latching comparators relates to the time required for input and reference voltages to recharge the input capacitances of the input amplifier since these capacitances are charged to a large negative voltage during the second portion of the clock cycle when the input amplifier is off. This charging time limits the frequency of operation of the circuit by placing a lower limit on the length of the first portion of the clock cycle. Another problem relates to "strobe kickout", a transient signal at the first stage input due to charging or discharging of the parasitic capacitance associated with the first stage when the bias current is switched on or off.
What is needed, and would be useful, is a high frequency latching comparator having minimal response delay due to input capacitance charging time and exhibiting minimal strobe kickout.